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<title>SUBSS—Subtract Scalar Single-Precision Floating-Point Value </title></head>
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<h1>SUBSS—Subtract Scalar Single-Precision Floating-Point Value</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op /En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>
<p>F3 0F 5C /r</p>
<p>SUBSS xmm1, xmm2/m32</p></td>
<td>RM</td>
<td>V/V</td>
<td>SSE</td>
<td>Subtract the low single-precision floating-point value in xmm2/m32 from xmm1 and store the result in xmm1.</td></tr>
<tr>
<td>
<p>VEX.NDS.128.F3.0F.WIG 5C /r</p>
<p>VSUBSS xmm1,xmm2, xmm3/m32</p></td>
<td>RVM</td>
<td>V/V</td>
<td>AVX</td>
<td>Subtract the low single-precision floating-point value in xmm3/m32 from xmm2 and store the result in xmm1.</td></tr>
<tr>
<td>
<p>EVEX.NDS.LIG.F3.0F.W0 5C /r</p>
<p>VSUBSS xmm1 {k1}{z}, xmm2, xmm3/m32{er}</p></td>
<td>T1S</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Subtract the low single-precision floating-point value in xmm3/m32 from xmm2 and store the result in xmm1 under writemask k1.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>RM</td>
<td>ModRM:reg (r, w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>RVM</td>
<td>ModRM:reg (w)</td>
<td>VEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr>
<tr>
<td>T1S</td>
<td>ModRM:reg (w)</td>
<td>EVEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr></table>
<p><strong>Description</strong></p>
<p>Subtract the low single-precision floating-point value from the second source operand and the first source operand and store the double-precision floating-point result in the low doubleword of the destination operand.</p>
<p>The second source operand can be an XMM register or a 32-bit memory location. The first source and destination operands are XMM registers.</p>
<p>128-bit Legacy SSE version: The destination and first source operand are the same. Bits (MAX_VL-1:32) of the corresponding destination register remain unchanged.</p>
<p>VEX.128 and EVEX encoded versions: Bits (127:32) of the XMM register destination are copied from corresponding bits in the first source operand. Bits (MAX_VL-1:128) of the destination register are zeroed.</p>
<p>EVEX encoded version: The low doubleword element of the destination operand is updated according to the writemask.</p>
<p>Software should ensure VSUBSS is encoded with VEX.L=0. Encoding VSUBSD with VEX.L=1 may encounter unpre-dictable behavior across different processor generations.</p>
<p><strong>Operation</strong></p>
<p><strong>VSUBSS (EVEX encoded version)</strong></p>
<p>IF (SRC2 *is register*) AND (EVEX.b = 1)</p>
<p>THEN</p>
<p>SET_RM(EVEX.RC);</p>
<p>ELSE</p>
<p>SET_RM(MXCSR.RM);</p>
<p>FI;</p>
<p>IF k1[0] or *no writemask*</p>
<p>THEN</p>
<p>DEST[31:0] (cid:197) SRC1[31:0] - SRC2[31:0]</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[31:0] remains unchanged*</p>
<p>ELSE</p>
<p>; zeroing-masking</p>
<p>THEN DEST[31:0] (cid:197) 0</p>
<p>FI;</p>
<p>FI;</p>
<p>DEST[127:32] (cid:197) SRC1[127:32]</p>
<p>DEST[MAX_VL-1:128] (cid:197) 0</p>
<p><strong>VSUBSS (VEX.128 encoded version)</strong></p>
<p>DEST[31:0] (cid:197)SRC1[31:0] - SRC2[31:0]</p>
<p>DEST[127:32] (cid:197)SRC1[127:32]</p>
<p>DEST[MAX_VL-1:128] (cid:197)0</p>
<p><strong>SUBSS (128-bit Legacy SSE version)</strong></p>
<p>DEST[31:0] (cid:197)DEST[31:0] - SRC[31:0]</p>
<p>DEST[MAX_VL-1:32] (Unmodified)</p>
<p><strong>Intel C/C++ Compiler Intrinsic Equivalent</strong></p>
<p>VSUBSS __m128 _mm_mask_sub_ss (__m128 s, __mmask8 k, __m128 a, __m128 b);</p>
<p>VSUBSS __m128 _mm_maskz_sub_ss (__mmask8 k, __m128 a, __m128 b);</p>
<p>VSUBSS __m128 _mm_sub_round_ss (__m128 a, __m128 b, int);</p>
<p>VSUBSS __m128 _mm_mask_sub_round_ss (__m128 s, __mmask8 k, __m128 a, __m128 b, int);</p>
<p>VSUBSS __m128 _mm_maskz_sub_round_ss (__mmask8 k, __m128 a, __m128 b, int);</p>
<p>SUBSS __m128 _mm_sub_ss (__m128 a, __m128 b);</p>
<p><strong>SIMD Floating-Point Exceptions</strong></p>
<p>Overflow, Underflow, Invalid, Precision, Denormal</p>
<p><strong>Other Exceptions</strong></p>
<table>
<tr>
<td>VEX-encoded instructions, see Exceptions Type 3.</td></tr>
<tr>
<td>EVEX-encoded instructions, see Exceptions Type E3.</td></tr></table></body></html>